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i 2 c-compatible, 256-position digital potentiometers ad5241/ad5242 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2009 analog devices, inc. all rights reserved. features 256 positions 10 k, 100 k, 1 m low temperature coefficient: 30 ppm/c internal power on midscale preset single-supply 2.7 v to 5.5 v or dual-supply 2.7 v for ac or bipolar operation i 2 c-compatible interface with readback capability extra programmable logic outputs self-contained shutdown feature extended temperature range: ?40c to +105c applications multimedia, video, and audio communications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion line impedance matching functional block diagram rdac register 1 addr decode 8 pwr-on reset serial input register ad5241 shdn v dd v ss sda scl gnd a 1 w 1 b 1 o 1 o 2 register 2 ad0 ad1 00926-001 figure 1. ad5241 functional block diagram a 1 w 1 b 1 a 2 w 2 b 2 o 1 o 2 rdac register 1 addr decode 8 pwr-on reset serial input register ad5242 v dd v ss sda scl gnd rdac register 2 register 1 ad0 ad1 00926-002 shdn figure 2. ad5242 functional block diagram general description the ad5241/ad5242 provide a single-/dual-channel, 256- position, digitally controlled variable resistor (vr) device. these devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. each vr offers a completely programmable value of resistance between the a terminal and the wiper, or the b terminal and the wiper. for the ad5242, the fixed a-to-b terminal resistance of 10 k, 100 k, or 1 m has a 1% channel-to-channel matching tolerance. the nominal temperature coefficient of both parts is 30 ppm/c. wiper position programming defaults to midscale at system power on. when powered, the vr wiper position is programmed by an i 2 c?-compatible, 2-wire serial data interface. both parts have two extra programmable logic outputs available that enable users to drive digital loads, logic gates, led drivers, and analog switches in their system. the ad5241/ad5242 are available in surface-mount, 14-lead soic and 16-lead soic packages and, for ultracompact solutions, 14-lead tssop and 16-lead tssop packages. all parts are guaranteed to operate over the extended temperature range of ?40c to +105c.
ad5241/ad5242 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 10 k, 100 k, 1 m version .................................................... 3 ? timing diagrams .......................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? test circuits ..................................................................................... 11 ? theory of operation ...................................................................... 12 ? programming the variable resistor ......................................... 12 ? programming the potentiometer divider ............................... 13 ? digital interface .......................................................................... 13 ? readback rdac value .............................................................. 14 ? multiple devices on one bus ................................................... 14 ? level-shift for bidirectional interface ..................................... 14 ? additional programmable logic output ................................ 15 ? shutdown function .................................................................... 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 18 ? revision history 12/09rev. b to rev. c changes to features section............................................................ 1 changes to 10 k, 100 k, 1 m version section ...................... 3 changes to table 3 ............................................................................ 6 deleted digital potentiometer selection guide section ........... 14 changed self-contained shutdown function section to shutdown function section .......................................................... 15 changes to shutdown function section ..................................... 15 changes to ordering guide .......................................................... 18 8/02rev. a to rev. b additions to features ....................................................................... 1 changes to general description .................................................... 1 changes to specifications ................................................................ 2 changes to absolute maximum ratings ....................................... 4 additions to ordering guide .......................................................... 4 changes to tpc 8 and tpc 9 ......................................................... 8 changes to readback rdac value section ................................ 11 changes to additional programmable logic output section .. 11 added self-contained shutdown section ................................... 12 added figure 8 ................................................................................ 12 changes to digital potentiometer selection guide ................... 14 2/02rev. 0 to rev. a edits to features ................................................................................. 1 edits to functional block diagrams ............................................... 1 edits to absolute maximum ratings .............................................. 4 changes to ordering guide ............................................................. 4 edits to pin function descriptions ................................................. 5 edits to figures 1, 2, 3 ....................................................................... 6 added readback rdac value section, additional programmable logic output section, and figure 7; renumbered sequentially ............................................................. 11 changes to digital potentiometer selection guide ................... 14
ad5241/ad5242 rev. c | page 3 of 20 specifications 10 k, 100 k, 1 m version v dd = 2.7 v to 5.5 v, v a = v dd , v b = 0 v, ?40c < t a < +105c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode (specifications apply to all vrs) resolution n 8 bits resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1 0.4 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?2 0.5 +2 lsb nominal resistor tolerance r ab /r ab t a = 25c, r ab = 10 k ?30 +30 % t a = 25c, r ab = 100 k/1 m ?30 +50 % resistance temperature coefficient (r ab /r ab )/ t 10 6 v ab = v dd , wiper = no connect 30 ppm/c wiper resistance r w i w = v dd /r 60 120 dc characteristi c s, potentiometer divide r mode (specifications apply to all vrs) resolution n 8 bits differential nonlinearity 3 dnl ?1 0.4 +1 lsb integral nonlinearity 3 inl ?2 0.5 +2 lsb voltage divider temperature coefficient (v w /v w )/?t 10 6 code = 0x80 5 ppm/c full-scale error v wfse code = 0xff ?1 ?0.5 0 lsb zero-scale error v wzse code = 0x00 0 0.5 1 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance (a, b) 5 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance (w) 5 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf common-mode leakage i cm v a = v b = v w 1 na digital inputs input logic high (sda and scl) v ih 0.7 v dd v dd + 0.5 v v input logic low (sda and scl) v il ?0.5 +0.3 v dd v input logic high (ad0 and ad1) v ih v dd = 5 v 2.4 v dd v input logic low (ad0 and ad1) v il v dd = 5 v 0 0.8 v input logic high v ih v dd = 3 v 2.1 v dd v input logic low v il v dd = 3 v 0 0.6 v input current i il v ih = 5 v or v il = gnd 1 a input capacitance 5 c il 3 pf digital output v ol i ol = 3 ma 0.4 v output logic low (sda) v ol i ol = 6 ma 0.6 v output logic low (o 1 and o 2 ) v ol i sink = 1.6 ma 0.4 v output logic high (o 1 and o 2 ) v oh i source = 40 a 4 v three-state leakage current (sda) i oz v ih = 5 v or v il = gnd 1 a output capacitance 5 c oz 3 8 pf power supplies power single-supply range v dd range v ss = 0 v 2.7 5.5 v power dual-supply range v dd /v ss range 2.3 2.7 v positive supply current i dd v ih = 5 v or v il = gnd 0.1 50 a negative supply current i ss v ss = ?2.5 v, v dd = +2.5 v +0.1 ?50 a power dissipation 6 p diss v ih = 5 v or v il = gnd, v dd = 5 v 0.5 250 w power supply sensitivity pss ?0.01 +0.002 +0.01 %/%
ad5241/ad5242 rev. c | page 4 of 20 parameter symbol conditions min typ 1 max unit dynamic characteristics 5 , 7 , 8 ?3 db bandwidth bw_10 k r ab = 10 k, code = 0x80 650 khz bw_100 k r ab = 100 k, code = 0x80 69 khz bw_1 m r ab = 1 m, code = 0x80 6 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.005 % v w settling time t s v a = v dd , v b = 0 v, 1 lsb error band, r ab = 10 k 2 s resistor noise voltage e n_wb r wb = 5 k, f = 1 khz 14 nvhz interface timing characteristics (applies to all parts 5 , 9 ) scl clock frequency f scl 0 400 khz bus free time between stop and start, t buf t 1 1.3 s hold time (repeated start), t hd; sta t 2 after this period, the first clock pulse is generated 600 ns low period of scl clock, t low t 3 1.3 s high period of scl clock, t high t 4 0.6 50 s setup time for repeated start condition, t su; sta t 5 600 ns data hold time, t hd; dat t 6 900 ns data setup time, t su; dat t 7 100 ns rise time of both sda and scl signals, t r t 8 300 ns fall time of both sda and scl signals, t f t 9 300 ns setup time for stop condition, t su; sto t 10 1 typicals represent average readings at 25c, v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see test circuits. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 37. 4 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 5 guaranteed by design, not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 8 all dynamic characteristics use v dd = 5 v. 9 see timing diagram in figure 3 fo r location of measured values.
ad5241/ad5242 rev. c | page 5 of 20 timing diagrams t 8 t 1 t 8 t 3 t 2 t 2 t 9 t 5 s d a scl t 10 s p t 7 t 4 sp t 6 0 0926-005 figure 3. detail timing diagram data of ad5241/ad5242 is accepted from the i 2 c bus in the following serial format. table 2. s 0 1 0 1 1 ad1 ad0 r/ w a a /b rs sd o 1 o 2 x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte where: s = start condition p = stop condition a = acknowledge x = dont care ad1, ad0 = package pin programmable address bits. must be matched with the logic states at pins ad1 and ad0. r/ w = read enable at high and output to sda. write enable at low. a /b = rdac subaddress select; 0 for rdac1 and 1 for rdac2. rs = midscale reset, active high. sd = shutdown in active high. same as shdn except inverse logic. o 1 , o 2 = output logic pin latched values d7, d6, d5, d4, d3, d2, d1, d0 = data bits. 1 1 19 9 9 0 1 0 1 a/b d0 d4 d5 d6d7 d3 d2 d1 ack by ad5241 ack by ad5241 ack by ad5241 stop by master s tart by master frame 1 slave address byte frame 2 instruction byte frame 3 data byte sda 1 ad1 ad0 r/w scl xxx 21 sd rs 00926-006 oo figure 4. writing to the rdac serial register 1 9 19 0 1 0 11 d7 ack by ad5241 no ack by master stop by master start by master frame 1 slave address byte frame 2 data byte from previously selected rdac register in write mode scl sda d6 d5 d4 d3 d2 d1 d0 ad1 ad0 r/w 0 0926-007 figure 5. reading data from a previously selected rdac register in write mode
ad5241/ad5242 rev. c | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ss to gnd 0 v to ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss to v dd i a , i b , i w r ab = 10 k in tssop-14 5.0 ma 1 r ab = 100 k in tssop-14 1.5 ma 1 r ab = 1 m in tssop-14 0.5 ma 1 digital input voltage to gnd 0 v to v dd + 0.3 v operating temperature range ?40c to +105c thermal resistance ja 14-lead soic 158c/w 16-lead soic 73c/w 14-lead tssop 206c/w 16-lead tssop 180c/w maximum junction temperature (t j max) 150c package power dissipation p d = (t j max ? t a )/ ja storage temperature range ?65c to +150c lead temperature vapor phase, 60 sec 215c infrared, 15 sec 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 maximum current increases at lower resistance and different packages.
ad5241/ad5242 rev. c | page 7 of 20 pin configurations and function descriptions top view (not to scale) 14 1 nc = no connect w 1 b 1 v dd shdn scl sda o 1 nc o 2 v ss dgnd ad1 ad0 a 1 ad5241 2 3 4 5 6 7 13 12 11 10 9 8 00926-003 figure 6. ad5241 pin configuration top view (not to scale) 1 o 1 a 1 w 1 b 1 v dd shdn scl sda a 2 w 2 b 2 o 2 v ss dgnd ad1 ad0 ad5242 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 00926-004 figure 7. ad5242 pin configuration table 4. ad5241 pin function descriptions pin o. neonic description 1 a 1 resistor terminal a 1 . 2 w 1 wiper terminal w 1 . 3 b 1 resistor terminal b 1 . 4 v dd positive power supply, specified for operation from 2.2 v to 5.5 v. 5 shdn active low, asynchronous connection of wiper w to terminal b, and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v dd if not used. 6 scl serial clock input. 7 sda serial data input/output. 8 ad0 programmable address bit for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 9 ad1 programmable address bit for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 10 dgnd common ground. 11 v ss negative power supply, specified for operation from 0 v to ?2.7 v. 12 o 2 logic output terminal o 2 . 13 nc no connect. 14 o 1 logic output terminal o 1 . table 5. ad5242 pin function descriptions pin o. neonic description 1 o 1 logic output terminal o 1 . 2 a 1 resistor terminal a 1 . 3 w 1 wiper terminal w 1 . 4 b 1 resistor terminal b 1 . 5 v dd positive power supply, specified for operation from 2.2 v to 5.5 v. 6 shdn active low, asynchronous connection of wiper w to terminal b, and open circuit of terminal a. rdac register contents unchanged. shdn should tie to v dd , if not used. 7 scl serial clock input. 8 sda serial data input/output. 9 ad0 programmable address bit for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 10 ad1 programmable address bit for multiple package decoding. bit ad0 and bit ad1 provide four possible addresses. 11 dgnd common ground. 12 v ss negative power supply, specified for operation from 0 v to ?2.7 v. 13 o 2 logic output terminal o 2 . 14 b 2 resistor terminal b 2 . 15 w 2 wiper terminal w 2 . 16 a 2 resistor terminal a 2 .
ad5241/ad5242 rev. c | page 8 of 20 typical performance characteristics code (decimal) 1.0 0.5 0 ?0.5 ?1.0 r h e o s t a t m o d e d if f e r e n t ia l n o n l in e a r it y (l s b ) 256 224 192 160 128 966432 0 v dd /v ss = +2.7v/0v v dd /v ss = +5.5v/0v, 2.7v v dd = +2.7v v dd = +5.5v v dd = 2.7v 0 0926-008 figure 8. rdnl vs. code code (decimal) 1.0 0.5 0 ?0.5 ?1.0 224 192 160 128 96 64 32 0 256 v dd /v ss = +2.7v/0v v dd /v ss = +5.5v/0v, 2.7v v dd = +2.7v v dd = +5.5v v dd = 2.7v r h e o s t a t m o d e in t e g r a l n o n l in e a r it y (l s b ) 0 0926-009 figure 9. rinl vs. code code (decimal) 0.25 0.13 0 ?0.13 ?0.25 p o t e n t io m e t e r m o d e d if f e r e n t ia l n o n l in e a r it y (l s b ) 256 224 192 160 128 966432 0 v dd = +2.7v v dd = +5.5v v dd = 2.7v v dd /v ss = +2.7v/0v, +5.5v/0v, 2.7v 00926-010 figure 10. dnl vs. code code (decimal) 0.50 0.25 0 ?0.25 ?0.50 p o t e n t io m e t e r m o d e in t e g r a l n o n l in e a r it y (l s b ) 256 224 160 128 64 32 01 96 9 2 v dd /v ss = +2.7v v dd /v ss = +2.7v/0v, +5.5v/0v v dd = +2.7v v dd = +5.5v v dd = 2.7v 00926-011 figure 11. inl vs. code 10k 100 1 n o m in a l r e s is t a n c e (k ? ) 80 60 40 20 0 ?20 ?40 temperature (c) v dd = 2.7v t a = 25c 10 1k 10k ? 100k ? 1m ? 00926-012 figure 12. nominal resistance vs. temperature 10k 1k 100 10 1 i d d s u p p l y c u r r e n t ( a ) 5 4 3 2 1 0 input logic voltage (v) v dd = 2.5v v dd = 3v v dd = 5v 00926-013 figure 13. supply current vs. input logic voltage
ad5241/ad5242 rev. c | page 9 of 20 0.1 0.01 0.001 s h u t d o w n c u r r e n t ( a ) 80 60 40 20 0 ?20 ?40 temperature (c) r ab = 10k ? v dd = 5.5v 0 0926-014 figure 14. shutdown current vs. temperature 100k ? version code (decimal) 128 966432 0 70 60 20 0 ?30 50 40 30 10 ?10 ?20 10k? version 10m ? version 160 192 224 256 v dd /v ss = 2.7v/0v t a = 25c potentiometer mode tempco (ppm/c) 0 0926-015 figure 15. v wb /t potentiometer mode temperature coefficient code (decimal) 120 100 20 ?20 ?80 r h e o s t a t m o d e t e m p c o (p p m /c ) 256 224 192 160 128 966432 0 80 60 40 0 ?40 ?60 10k ? version 10m ? version 100k ? version v dd /v ss = 2.7v/0v t a = 25c 00926-016 figure 16. r wb /t rheostat mode temperature coefficient t a = 25c common-mode (v) 100 90 50 30 w ip e r r e s is t a n c e ( ? ) 543210 ?1?2?3 80 70 60 40 20 10 v dd /v ss = +2.7v/0v 6 v dd /v ss = 2.7v/0v v dd /v ss = +5.5v/0v 00926-017 figure 17. incremental wiper contact vs. v dd /v ss frequency (khz) 300 100 50 0 i d d s u p p l y c u r r e n t ( a ) 1k 100 10 150 200 250 e b c a d f a: v dd /v ss = 5.5v/0v code = 0xff b: v dd /v ss = 3.3v/0v code = 0xff c: v dd /v ss = 2.5v/0v code = 0xff d: v dd /v ss = 5.5v/0v code = 0x55 e: v dd /v ss = 3.3v/0v code = 0x55 f: v dd /v ss = 2.5v/0v code = 0x55 00926-018 figure 18. supply current vs. frequency frequency (hz) 6 ?36 ?42 ?48 ?54 g a in (d b ) 1m 100k 10k 1k 100 ?30 ?24 ?18 ?12 ?6 0 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 00926-019 figure 19. ad5242 10 k gain vs. frequency vs. code
ad5241/ad5242 rev. c | page 10 of 20 frequency (hz) 6 ?36 ?42 ?48 ?54 100k 10k 1k 100 ?30 ?24 ?18 ?12 ?6 0 g a in (d b ) 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 00926-020 figure 20. ad5242 100 k gain vs. frequency vs. code frequency (hz) 6 ?36 ?42 ?48 ?54 g a in (d b ) 100k 10k 1k 100 ?30 ?24 ?18 ?12 ?6 0 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 00926-021 figure 21. ad5242 1 m gain vs. frequency vs. code
ad5241/ad5242 rev. c | page 11 of 20 test circuits figure 22 to figure 30 define the test conditions used in the product specifications table. v ms a w b dut 0 0926-029 v+ v+ = v dd 1 lsb = v+/2 n figure 22. potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut 00926-030 figure 23. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w a w b dut r w = [v ms1 ? v ms2 ]/i w 00926-031 figure 24. wiper resistance v dd % v ms % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v dd v a v ms a w b v+ v dd v ms 0 0926-032 figure 25. power supply sensitivity (pss, psrr) 00926-033 op279 w 5v b v out offset gnd offset bias a dut figure 26. inverting gain b a v in op279 w 5 v v out offset gnd offset bias dut 00926-034 figure 27. noninverting gain +15v ?15v w a 2.5v b v out o ffset gnd dut op42 v in 00926-035 figure 28. gain vs. frequency w b dut i sw code = 0x00 r sw = 0.1 v i sw 0.1v v ss to v dd 00926-036 figure 29. incremental on resistance w b v cm i cm a nc gnd nc v ss v dd dut 00926-037 figure 30. common-mode leakage current
ad5241/ad5242 rev. c | page 12 of 20 theory of operation the ad5241/ad5242 provide a single-/dual-channel, 256- position digitally controlled variable resistor (vr) device. the terms vr, rdac, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. to program the vr settings, refer to the digital interface section. both parts have an internal power-on preset that places the wiper in midscale during power-on that simplifies the fault condition recovery at power-up. in addition, the shutdown pin ( shdn ) of ad5241/ad5242 places the rdac in an almost zero power consumption state where terminal a is open circuited and wiper w is connected to terminal b, resulting in only leakage current being consumed in the vr structure. during shutdown, the vr latch contents are maintained when the rdac is inactive. when the part returns from shutdown, the stored vr setting is applied to the rdac. sw shdn sw n 2?1 r r sw n 2?2 rdac latch and decoder rr ab /2 n b w digital circuitry omitted for clarity a sw 1 sw 0 r r d7 d6 d5 d4 d3 d2 d1 d0 shdn 00926-022 figure 31. equivalent rdac circuit programming the variable resistor rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available in 10 k, 100 k, and 1 m. the final two or three digits of the part number determine the nominal resistance value, for example, 10 k = 10, 100 k = 100, and 1 m = 1 m. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assume a 10 k part is used; the first connection of the wiper starts at the b terminal for data 0x00. because there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between terminal w and terminal b. the second connection is the first tap point that corresponds to 99 (r wb = r ab /256 + r w = 39 + 60) for data 0x01. the third connection is the next tap point representing 138 (39 2 + 60) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,021 [r ab C 1 lsb + r w ]. figure 31 shows a simplified diagram of the equivalent rdac circuit where the last resistor string is not accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. the general equation determining the digitally programmed resistance between w and b is r wb ( d ) = 256 d r ab + r w (1) where: d is the decimal equivalent of the binary code between 0 and 255, which is loaded in the 8-bit rdac register. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. again, if r ab = 10 k, terminal a can be either open circuit or tied to w. table 6 shows the r wb resistance based on the code set in the rdac latch. table 6. r wb (d) at selected codes for r ab = 10 k d (dec) r wb () output state 255 10021 full-scale (r wb C 1 lsb + r w ) 128 5060 midscale 1 99 1 lsb 0 60 zero-scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 60 is present. care should be taken to limit the current flow between w and b in this state to a maximum current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled resistance, r wa . when these terminals are used, terminal b can be opened or tied to the wiper terminal. the minimum r wa resistance is for data 0xff and increases as the data loaded in the latch decreases in value. the general equation for this operation is r wa ( d) = 256 256 d ? r ab + r w (2) for r ab = 10 k, terminal b can be either open circuit or tied to w. table 7 shows the r wa resistance based on the code set in the rdac latch. table 7. r wa (d) at selected codes for r ab = 10 k d (dec) r wa () output state 255 99 full-scale 128 5060 midscale 1 10021 1 lsb 0 10060 zero-scale
ad5241/ad5242 rev. c | page 13 of 20 the typical distribution of the nominal resistance r ab from channel to channel matches within 1% for ad5242. device- to-device matching is process lot dependent, and it is possible to have 30% variation. because the resistance element is processed in thin film technology, the change in r ab with temperature has no more than a 30 ppm/c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper-to-b and wiper-to-a to be proportional to the input voltage at a-to-b. unlike the polarity of v dd /v ss , which must be positive, voltage across terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b can be at either polarity provided that v ss is powered by a negative supply. if ignoring the effect of the wiper resistance for approximation, connecting terminal a to 5 v and terminal b to ground produces an output voltage at the wiper-to-b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 positions of the potentiometer divider. because ad5241/ad5242 can be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is () b a w v d v d dv 256 256 256 ? += (3) which can be simplified to () b ab w vv d dv += 256 (4) where d is the decimal equivalent of the binary code between 0 to 255 that is loaded in the 8-bit rdac register. for a more accurate calculation, including the effects of wiper resistance, v w can be found as () b ab wa a ab wb w v r dr v r dr dv )( )( + = (5) where r wb ( d ) and r wa ( d ) can be obtained from equation 1 and equation 2. operation of the digital potentiometer in divider mode results in a more accurate operation over temperature. unlike rheostat mode, the output voltage is dependent on the ratio of the internal resistors, r wa and r wb , and not the absolute values; therefore, the temperature drift reduces to 5 ppm/c. digital interface 2-wire serial bus the ad5241/ad5242 are controlled via an i 2 c-compatible serial bus. the rdacs are connected to this bus as slave devices. referring to figure 3 and figure 4 , the first byte of ad5241/ ad5242 is a slave address byte. it has a 7-bit slave address and an r/ w bit. the five msbs are 01011 and the following two bits are determined by the state of the ad0 and ad1 pins of the device. ad0 and ad1 allow users to use up to four of these devices on one bus. the 2-wire, i 2 c serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 4 ). the following byte is the frame 1, slave address byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. 2. a write operation contains an extra instruction byte more than the read operation. the frame 2 instruction byte in write mode follows the slave address byte. the msb of the instruction byte labeled a /b is the rdac subaddress select. a low selects rdac1 and a high selects rdac2 for the dual- channel ad5242. set a /b to low for the ad5241. the second msb, rs, is the midscale reset. a logic high of this bit moves the wiper of a selected rdac to the center tap where r wa = r wb . the third msb, sd, is a shutdown bit. a logic high on sd causes the rdac to open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost a 0 rheostat mode or 0 v in potentiometer mode. this sd bit serves the same function as the shdn pin except that the shdn pin reacts to active low. the following two bits are o 2 and o 1 . they are extra programmable logic outputs that users can use to drive other digital loads, logic gates, led drivers, analog switches, and the like. the three lsbs are dont care (see ). figure 4 3. after acknowledging the instruction byte, the last byte in write mode is the, frame 3 data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 4 ).
ad5241/ad5242 rev. c | page 14 of 20 4. unlike the write mode, the data byte follows immediately after the acknowledgment of the slave address byte in frame 2 read mode. data is transmitted over the serial bus in sequences of nine clock pulses (slightly different from the write mode, there are eight data bits followed by a no acknowledge logic 1 bit in read mode). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 5 ). multiple devices on one bus figure 33 shows four ad5242 devices on the same serial bus. each has a different slave address because the state of their ad0 and ad1 pins are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c-compatible interface. note, a device is addressed properly only if the bit information of ad0 and ad1 in the slave address byte matches with the logic inputs at the ad0 and ad1 pins of that particular device. 5. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the tenth clock pulse to establish a stop condition (see figure 4 ). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the tenth clock pulse, which goes high to establish a stop condition (see figure 5 ). level-shift for bidirectional interface while most old systems can operate at one voltage, a new component may be optimized at another. when they operate the same signal at two different voltages, a proper method of level-shifting is needed. for instance, a 3.3 v e 2 prom can be used to interface with a 5 v digital potentiometer. a level-shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the e 2 prom. figure 32 shows one of the techniques. m1 and m2 can be n-channel fets (2n7002) or low threshold fdv301n if v dd falls below 2.5 v. a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. during the write cycle, each data byte updates the rdac output. for example, after the rdac has acknowledged its slave address and instruction bytes, the rdac output is updated. if another byte is written to the rdac while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. if different instructions are needed, the write mode has to start a completely new sequence with a new slave address, instruction, and data bytes transferred again. similarly, a repeated read function of the rdac is also allowed. r p r p sd sd g m1 g m2 3.3v e 2 prom r p r p 5v ad5242 scl2 sda2 v dd = 5 v v dd = 3.3 v scl1 sda1 0 0926-024 figure 32. level-shift for different voltage devices operation readback rdac value specific to the ad5242 dual-channel device, the channel of interest is the one that was previously selected in the write mode. in addition, to read both rdac values consecutively, users have to perform two write-read cycles. for example, users may first specify the rdac1 subaddress in write mode (it is not necessary to issue the data byte and stop condition), and then change to read mode to read the rdac1 value. to continue reading the rdac2 value, users have to switch back to write mode, specify the subaddress, and then switch once again to read mode to read the rdac2 value. it is not necessary to issue the write mode data byte or the first stop condition for this operation. users should refer to figure 4 and figure 5 for the programming format. sda scl ad5242 ad1 ad0 sda scl r p r p sda scl ad5242 v dd ad1 ad0 sda scl ad1 ad0 ad5242 v dd sda scl ad5242 v dd ad1 ad0 master 5 v 0 0926-023 figure 33. multiple ad5242 devices on one bus
ad5241/ad5242 rev. c | page 15 of 20 additional programmable logic output the ad5241/ad5242 feature additional programmable logic outputs, o 1 and o 2 , that can be used to drive digital load, analog switches, and logic gates. they can also be used as a self-contained shutdown preset to logic 0 that is further explained in the shutdown function section. o 1 and o 2 default to logic 0 during power-up. the logic states of o 1 and o 2 can be programmed in frame 2 under the write mode (see figure 4 ). figure 34 shows the output stage of o 1 , which employs large p-channel and n- channel mosfets in push-pull configuration. as shown in figure 34 , the output is equal to v dd or v ss , and these logic outputs have adequate current driving capability to drive milliamperes of load. in 1 2 v dd o 1 v ss m p m n o 1 data in frame 2 of write mode 00926-025 fi gure 34. output stage of logic output, o 1 us ers can also activate o 1 and o 2 in the following three different ways without affecting the wiper settings: 1. start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. 2. complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. 3. do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. all digital inputs are protected with a series input resistor and the parallel zener esd structures shown in figure 36 . this applies to the digital input pins, sda, scl, and shdn . shutdown function shutdown can be activated by strobing the shdn pin or programming the sd bit in the write mode instruction byte (see ). if the rdac register 1 or rdac register 2 (ad5242 only) is placed in shutdown mode by the software, sd bit, the part returns the wiper to its prior position when a new command is received. table 2 in addition, shutdown can be implemented with the device digital output, as shown in figure 35 . in this configuration, the device is shutdown during power-up but users are allowed to program the device. thus, when o 1 is programmed high, the device exits shutdown mode and responds to the new setting. this self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, and it does not add extra components. sda shdn scl r pd o 1 0 0926-026 figure 35. shutdown by internal logic output, o 1 340 ? logic v ss 00926-027 figure 36. esd protection of digital pins a ,b,w v ss 00926-028 figure 37. esd protection of resistor terminals
ad5241/ad5242 rev. c | page 16 of 20 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 38. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 39. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches)
ad5241/ad5242 rev. c | page 17 of 20 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 40. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 41. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches)
ad5241/ad5242 rev. c | page 18 of 20 ordering guide model 1 , 2 no. of channels end-to-end r ab temperature range package description package option ad5241br10 1 10 k C40c to +105c 14-lead soic_n r-14 ad5241br10-reel7 1 10 k C40c to +105c 14-lead soic_n r-14 ad5241brz10 1 10 k C40c to +105c 14-lead soic_n r-14 ad5241brz10-rl7 1 10 k C40c to +105c 14-lead soic_n r-14 AD5241BRU10 1 10 k C40c to +105c 14-lead tssop ru-14 AD5241BRU10-reel7 1 10 k C40c to +105c 14-lead tssop ru-14 ad5241bruz10 1 10 k C40c to +105c 14-lead tssop ru-14 ad5241bruz10-r7 1 10 k C40c to +105c 14-lead tssop ru-14 ad5241br100 1 100 k C40c to +105c 14-lead soic_n r-14 ad5241br100-reel7 1 100 k C40c to +105c 14-lead soic_n r-14 ad5241brz100 1 100 k C40c to +105c 14-lead soic_n r-14 ad5241brz100-rl7 1 100 k C40c to +105c 14-lead soic_n r-14 AD5241BRU100 1 100 k C40c to +105c 14-lead tssop ru-14 AD5241BRU100-reel7 1 100 k C40c to +105c 14-lead tssop ru-14 ad5241bruz100 1 100 k C40c to +105c 14-lead tssop ru-14 ad5241bruz100-r7 1 100 k C40c to +105c 14-lead tssop ru-14 ad5241br1m 1 1 m C40c to +105c 14-lead soic_n r-14 ad5241brz1m 1 1 m C40c to +105c 14-lead soic_n r-14 ad5241brz1m-reel 1 1 m C40c to +105c 14-lead soic_n r-14 ad5241bru1m 1 1 m C40c to +105c 14-lead soic_n r-14 ad5241bru1m-reel7 1 1 m C40c to +105c 14-lead tssop ru-14 ad5241bruz1m 1 1 m C40c to +105c 14-lead tssop ru-14 ad5241bruz1m-r7 1 1 m C40c to +105c 14-lead tssop ru-14 ad5242br10 2 10 k C40c to +105c 16-lead soic_n r-16 ad5242br10-reel7 2 10 k C40c to +105c 16-lead soic_n r-16 ad5242brz10 2 10 k C40c to +105c 16-lead soic_n r-16 ad5242brz10-reel7 2 10 k C40c to +105c 16-lead soic_n r-16 ad5242bru10 2 10 k C40c to +105c 16-lead tssop ru-16 ad5242bru10-reel7 2 10 k C40c to +105c 16-lead tssop ru-16 ad5242bruz10 2 10 k C40c to +105c 16-lead tssop ru-16 ad5242bruz10-rl7 2 10 k C40c to +105c 16-lead tssop ru-16 ad5242br100 2 100 k C40c to +105c 16-lead soic_n r-16 ad5242br100-reel7 2 100 k C40c to +105c 16-lead soic_n r-16 ad5242brz100 2 100 k C40c to +105c 16-lead soic_n r-16 ad5242brz100-reel7 2 100 k C40c to +105c 16-lead soic_n r-16 ad5242bru100 2 100 k C40c to +105c 16-lead tssop ru-16 ad5242bru100-reel7 2 100 k C40c to +105c 16-lead tssop ru-16 ad5242bruz100 2 100 k C40c to +105c 16-lead tssop ru-16 ad5242bruz100-rl7 2 100 k C40c to +105c 16-lead tssop ru-16 ad5242br1m 2 1 m C40c to +105c 16-lead soic_n r-16 ad5242brz1m 2 1 m C40c to +105c 16-lead soic_n r-16 ad5242bru1m 2 1 m C40c to +105c 16-lead soic_n r-16 ad5242bru1m-reel7 2 1 m C40c to +105c 16-lead tssop ru-16 ad5242bruz1m 2 1 m C40c to +105c 16-lead tssop ru-16 ad5242bruz1m-reel7 2 1 m C40c to +105c 16-lead tssop ru-16 eval-ad5242ebz 2 evaluation board 1 the ad5241/ad5242 die size is 69 mil 78 mil, 5,382 sq. mil. contains 386 transistors fo r each channel. patent number 5,495,2 45 applies. 2 z = rohs compliant part.
ad5241/ad5242 rev. c | page 19 of 20 notes
ad5241/ad5242 rev. c | page 20 of 20 notes ?2001C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00926-0-12/09(c)

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